Dynamic random access memories (DRAMs) enjoy wide application as storage circuits in electronic devices due to their compact cell size and relatively low power consumption. A typical conventional DRAM device can include an array of DRAM memory cells, each of which can be formed by a metal-oxide-semiconductor (MOS) type access transistor and a storage capacitor. In a write operation to a conventional DRAM cell, a storage capacitor can be charged via the source-drain path of the MOS access transistor to store one logic value (i.e., “1”), or discharged to store another logic value (i.e., “0”). To retain data, the MOS access transistor is turned off. In order to ensure that valid data continues to be stored, conventional DRAM cells must be periodically refreshed to account for leakage from the storage capacitors.
In a read operation, a MOS access transistor can be turned on, connecting the corresponding storage capacitor to a bit line. As a result, a potential change can occur on the bit line according to whether the corresponding storage capacitor is charged or not charged. Typically, a data value can be sensed by a MOS transistor based sense amplifier.
Conventionally, even in an off state, an access transistor can leak current from its corresponding storage capacitor. This can be particularly true as transistor sizes continue to shrink. Thus, to account for more leakage, refresh rates can be increased, thus increasing power consumption, and/or capacitor size can be increased. However, larger capacitor sizes require more integrated circuit (die) area, leading to increased cost per die.
In addition to MOS access transistor leakage, another drawback to conventional DRAM devices can be susceptibility to radiation induced events, sometimes referred to as “single event upset” (SEU). In particular, SEU can result in a change in threshold voltage of a MOS transistor. That is, SEU can result in undesirably large leakage in a MOS access transistor. To compensate for such an event, a storage capacitor size can be increased, but this can lead to increased costs, as noted above. In the case of a sense amplifier MOS transistor, an SEU event can cause a mismatch in otherwise matching transistors, which can lead to erroneous data sensing.